Building a 1-Bit Full Adder with Verilog and FPGA
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Time to read 5 min
Introduction
Among all digital circuits, the adder stands out as one of the most essential building blocks. It performs arithmetic operations that underpin every modern computing and processing unit. In this article, we will focus on the simplest yet complete version: the 1-bit full adder. You will explore its logic principles, implement it in Verilog, map it onto an FPGA, and finally validate the design through hands-on experiments. This project is also featured in Chapter 3 of Fundamental Digital Circuits and FPGAs, where the full learning kit is available.
Table of contents
What is HDL and Why Verilog Matters FPGA: The All-Rounder of Digital Circuit Design FPGA vs Microcontroller: A Beginner-Friendly Comparison FPGA Architecture at a Glance Verilog and FPGA Development From Code to Hardware: The FPGA Design Flow Development Tools and IDEs Learning Made Simple with Our STEPFPGA WebIDE A Complete Example: From Verilog to FPGA Digital Design with Verilog Example: Design a 3-by-8 Decoder More to Discover
Understanding the Role of Adders in Digital Systems
A half adder is the simplest arithmetic circuit. It adds two binary digits (A and B) and produces a Sum and a Carry. Unlike decimal numbers where digits range from 0 to 9, binary arithmetic uses only 0 and 1, so even the simplest addition can generate a carry into the next higher bit.
However, in real systems, addition usually involves more than just two bits. That is where the full adder comes in. The full adder extends the logic by including a third input, called the carry-in (Cin). This allows multiple adders to be chained together, enabling multi-bit addition.
The Logic of a 1-Bit Full Adder
Truth Table of a 1-bit Full Adder
The truth table clearly shows how all input combinations map to outputs. The 8 rows represent all possible cases of the three inputs (A, B and Carry): whenever two or more inputs are high, the carry output is triggered, while the sum output reflects the parity of the inputs.
Logic Gate Circuits and Boolean Functions
The full adder has three inputs (A, B, Cin) and two outputs (Sum and CO). The Boolean expression for each output is obtained as:
Sum = A ⊕ B ⊕ Cin
Co = (A ⊕ B)·Cin + A·B
The diagram on the right shows that the XOR gates form the Sum output and AND, OR combinations generate the Carry.
Forming a 4-bit Ripple Adder with four Full Adders
By connecting multiple 1-bit full adders, we create a ripple-carry adder. For example, four 1-bit adders chained together form a 4-bit adder capable of adding two 4-bit binary numbers. This is the stepping stone toward larger adders and entire arithmetic units.
Implementing the Full Adder in Verilog
Here we demonstrate two different styles of describing the same full adder in Verilog. The dataflow style (left) uses assign statements to directly express the Boolean equations, which makes the logic concise and efficient. The structural style (right), though a bit longer, mirrors the schematic diagram directly in code, showing how XOR, AND, and OR gates combine to form the Sum and Carry outputs of the full adder.
Now that you have seen both the dataflow and structural styles of implementing a full adder, we suggest running both versions in our webIDE to observe the results side by side. For more detailed guide, refer back to our earlier tutorial article, where we walk through project setup, simulation, and testing in detail.
Mapping the Full Adder on FPGA
If the Verilog code is correct, running it in the IDE will complete logic synthesis, which means the module has been successfully translated into a circuit where the input–output relationships are already defined. The next step is to map these logical signals to the physical pins of the FPGA, so that switches, buttons, and LEDs on the board can interact with your design.
As shown in the figure above, the inputs a, b, and cin are assigned to switches, while the outputs sum and co are mapped to LEDs. This mapping turns the abstract Verilog description into a tangible hardware experiment that you can test directly on your FPGA board.
Note: In this example, we mapped the module’s inputs and outputs directly to the board’s built-in peripherals, such as switches and LEDs, for quick verification. If you plan to connect external devices, you can use the external GPIO pins instead. In the book Chapters 5 and 6, we provided many such examples where onboard and external peripherals are combined for more advanced projects.
Adders to More Advanced Computing Systems
A single 1-bit full adder may seem basic, but when many of them are combined, they form multi-bit adders capable of handling larger binary numbers. These structures then serve as the foundation for higher-level components, enabling processors to execute not only addition, but also subtraction, multiplication, and more sophisticated operations.
Arithmetic Logic Unit
At the hardware level, adders are implemented inside the Arithmetic Logic Unit (ALU), the part of the processor responsible for carrying out arithmetic and logical instructions. The ALU is where abstract equations turn into physical operations on bits. In our upcoming learning kit, we dedicate a full section to exploring ALU design step by step. If you’d like to follow along, make sure to subscribe to our email updates to get notified as soon as it launches.
ALU in CPUs and GPUs
Zooming out to modern processors like CPUs and GPUs, the picture only becomes larger in scale. Both are built around massive networks of ALUs, executing billions of add, subtract, and multiply instructions every second. At the heart of those ALUs are still the same 1-bit and multi-bit adders you are learning today. In other words, by mastering a simple full adder, you are taking your first step into understanding the logic that drives entire computers and graphics processors.
Two major HDLs dominate the field: Verilog and VHDL. Both can model combinational and sequential logic, but Verilog has a syntax closer to C, which makes it more approachable for beginners and project-based learning. VHDL, on the other hand, is often considered more verbose but also highly structured and strict, which some engineers prefer for large-scale systems. For learners starting out with FPGA projects, Verilog is usually the smoother entry point while still being widely used in both academia and industry.
FAQs
What is the difference between a half adder and a full adder?
A half adder adds two binary inputs but cannot take a carry input. A full adder extends this by adding a carry-in, making it suitable for multi-bit addition when chained together.
Which Verilog style should I use—dataflow, structural, or behavioral?
All three work. Dataflow is concise, structural mirrors gate-level schematics, and behavioral can be easier to read for beginners. Try each in the webIDE to see the differences.
Can I extend a 1-bit full adder to design a 4-bit or 8-bit adder?
Yes. By cascading multiple 1-bit full adders, you can build a ripple-carry adder, which is usually the simplest form of multi-bit adders.
What are some limitations of ripple-carry adders?
Ripple-carry adders are simple, but they suffer from propagation delay as the carry signal ripples through each stage. More advanced designs use carry-lookahead or carry-select structures to speed up performance.
Can adders be used outside of arithmetic operations?
Yes. Adders also appear in digital signal processing, error detection/correction, cryptography, and even in hardware accelerators for AI.
Daniel Cao
Daniel Cao is the founder of EIM Technology, where he creates hands-on, beginner-friendly electronics education kits that blend practical hardware with clear, structured learning. With a background in engineering and a passion for teaching, he focuses on making complex concepts accessible to learners from all disciplines.
